View PIC16C712_4761.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PIC16C712/716
8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM
Devices included in this Data Sheet:
* PIC16C712 * PIC16C716
Pin Diagrams 18-pin PDIP, SOIC, Windowed CERDIP
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
Microcontroller Core Features:
* High-performance RISC CPU * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle Program Device Data Memory Memory PIC16C712 1K 128 PIC16C716 2K 128 * Interrupt capability (up to 7 internal/external interrupt sources) * Eight level deep hardware stack * Direct, indirect and relative addressing modes * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Brown-out detection circuitry for Brown-out Reset (BOR) * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options * Low-power, high-speed CMOS EPROM technology * Fully static design * In-Circuit Serial ProgrammingTM (ICSP) * Wide operating voltage range: 2.5V to 5.5V * High Sink/Source Current 25/25 mA * Commercial, Industrial and Extended temperature ranges * Low-power consumption: - < 2 mA @ 5V, 4 MHz - 22.5 A typical @ 3V, 32 kHz - < 1 A typical standby current
RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4
PIC16C712 PIC16C716
20-pin SSOP
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4
PIC16C712 PIC16C716
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler can be incremented during sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Capture, Compare, PWM module * Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit * 8-bit multi-channel Analog-to-Digital converter
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 1
PIC16C712/716
Key Features PICmicroTM Mid-Range Reference Manual (DS33023) Operating Frequency Resets (and Delays) Program Memory (14-bit words) Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM modules 8-bit Analog-to-Digital Module
PIC16C712 DC - 20 MHz POR, BOR (PWRT, OST) 1K 128 7 Ports A,B 3 1 4 input channels
PIC16C716 DC - 20 MHz POR, BOR (PWRT, OST) 2K 128 7 Ports A,B 3 1 4 input channels
PIC16C7XX FAMILY OF DEVICES
PIC16C710 Clock Maximum Frequency of Operation (MHz) EPROM Program Memory (x14 words) Data Memory (bytes) Timer Module(s) 20 512 PIC16C71 20 1K PIC16C711 20 1K PIC16C712 20 1K PIC16C715 20 2K PIC16C716 20 2K PIC16C72A 20 2K PIC16C73B 20 4K
Memory
36 TMR0
36 TMR0
68 TMR0
128 TMR0 TMR1 TMR2 1 -- 4 7 13 2.5-5.5 Yes Yes
128 TMR0
128 TMR0 TMR1 TMR2 1 -- 4 7 13 2.5-5.5 Yes Yes
128 TMR0 TMR1 TMR2 1 SPI/I2C 5 8 22 2.5-5.5 Yes Yes
192 TMR0 TMR1 TMR2 2 SPI/I2C, USART 5 11 22 2.5-5.5 Yes Yes
Capture/Compare/ Peripherals PWM Module(s) Serial Port(s) (SPI/I2C, USART) A/D Converter (8-bit) Channels Interrupt Sources I/O Pins Voltage Range (Volts) Features In-Circuit Serial Programming Brown-out Reset Packages
-- -- 4 4 13 2.5-6.0 Yes Yes 18-pin DIP, SOIC; 20-pin SSOP
-- -- 4 4 13 3.0-6.0 Yes --
-- -- 4 4 13 2.5-6.0 Yes Yes
-- -- 4 4 13 2.5-5.5 Yes Yes
18-pin DIP, 18-pin DIP, SOIC SOIC; 20-pin SSOP
18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC; SOIC; SOIC, SSOP SOIC 20-pin SSOP 20-pin SSOP 20-pin SSOP
DS41106A-page 2
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
Table of Contents
1.0 Device Overview.................................................................................................................................................. 5 2.0 Memory Organization .......................................................................................................................................... 9 3.0 I/O Ports ............................................................................................................................................................ 21 4.0 Timer0 Module................................................................................................................................................... 29 5.0 Timer1 Module................................................................................................................................................... 31 6.0 Timer2 Module................................................................................................................................................... 36 7.0 Capture/Compare/PWM (CCP) Module(s) ........................................................................................................ 39 8.0 Analog-to-Digital Converter (A/D) Module ......................................................................................................... 45 9.0 Special Features of the CPU ............................................................................................................................. 51 10.0 Instruction Set Summary ................................................................................................................................... 67 11.0 Development Support........................................................................................................................................ 69 12.0 Electrical Characteristics ................................................................................................................................... 75 13.0 DC and AC Characteristics Graphs and Tables ................................................................................................ 91 14.0 Packaging Information....................................................................................................................................... 93 Revision History ........................................................................................................................................................... 99 Conversion Considerations .......................................................................................................................................... 99 Migration from Base-line to Mid-Range Devices .......................................................................................................... 99 Index ........................................................................................................................................................................... 101 On-Line Support.......................................................................................................................................................... 105 Reader Response ....................................................................................................................................................... 106 PIC16C712/716 Product Identification System ........................................................................................................... 107
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: * Fill out and mail in the reader response form in the back of this data sheet. * E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 3
PIC16C712/716
NOTES:
DS41106A-page 4
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
1.0 DEVICE OVERVIEW
This document contains device-specific information. Additional information may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are two devices (PIC16C712, PIC16C716) covered by this datasheet. Figure 1-1 is the block diagram for both devices. The pinouts are listed in Table 1-1.
FIGURE 1-1:
PIC16C712/716 BLOCK DIAGRAM
13 EPROM 1K X 14 or 2K x 14 Program Memory Program Counter Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI
8 Level Stack (13-bit)
Program Bus
RAM 128 x 8 File Registers RAM Addr(1) 9 PORTB
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8 W reg ALU
RB0/INT RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1 RB4 RB5 RB6 RB7
MUX
MCLR
VDD, VSS
Timer0
Timer1
Timer2
CCP1
A/D
Note 1: Higher order bits are from the STATUS register.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 5
PIC16C712/716
TABLE 1-1
Pin Name MCLR/VPP MCLR VPP OSC1/CLKIN OSC1
PIC16C712/716 PINOUT DESCRIPTION
PIC16C712/716 DIP, SOIC 4 SSOP 4 I P 16 18 I ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. CMOS otherwise. External clock source input. ST Master clear (reset) input. This pin is an active low reset to the device. Programming voltage input Pin Type Buffer Type Description
CLKIN OSC2/CLKOUT OSC2 15 17
I
CMOS
O
--
CLKOUT
O
--
Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. PORTA is a bi-directional I/O port.
RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2 RA2 AN2 RA3/AN3/VREF RA3 AN3 VREF RA4/T0CKI RA4
17
19 I/O I TTL Analog TTL Analog TTL Analog TTL Analog Analog ST/OD Digital I/O Analog input 0 Digital I/O Analog input 1 Digital I/O Analog input 2 Digital I/O Analog input 3 A/D Reference Voltage input.
18
20 I/O I
1
1 I/O I
2
2 I/O I I
3
3 I/O
Digital I/O. Open drain when configured as output. T0CKI I ST Timer0 external clock input Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels OD = Open drain output SM = SMBus compatible input. An external resistor is required if this pin is used as an output NPU = N-channel pull-up PU = Weak internal pull-up AN = Analog input or output No-P diode = No P-diode to VDD I = input O = output P = Power L = LCD Driver
DS41106A-page 6
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
TABLE 1-1
Pin Name
PIC16C712/716 PINOUT DESCRIPTION (Cont.'d)
PIC16C712/716 DIP, SOIC SSOP Pin Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/INT RB0 INT RB1/T1OSO/T1CKI RB1 T1OSO T1CKI
6
7 I/O I TTL ST Digital I/O External Interrupt
7
8 I/O O I TTL -- ST TTL -- Digital I/O Timer1 oscillator output. Connects to crystal in oscillator mode. Timer1 external clock input. Digital I/O Timer1 oscillator input. Connects to crystal in oscillator mode.
RB2/T1OSI RB2 T1OSI RB3/CCP1 RB3 CCP1
8
9 I/O I
9
10 I/O I/O TTL ST
Digital I/O Capture1 input, Compare1 output, PWM1 output. RB4 10 12 I/O TTL Digital I/O Interrupt on change pin. RB5 11 12 I/O TTL Digital I/O Interrupt on change pin. RB6 12 13 I/O TTL Digital I/O Interrupt on change pin. I ST ICSP programming clock. RB7 13 14 I/O TTL Digital I/O Interrupt on change pin. I/O ST ICSP programming data. 5 5, 6 P -- Ground reference for logic and I/O pins. VSS 14 15, 16 P -- Positive supply for logic and I/O pins. VDD Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels OD = Open drain output SM = SMBus compatible input. An external resistor is required if this pin is used as an output NPU = N-channel pull-up PU = Weak internal pull-up AN = Analog input or output No-P diode = No P-diode to VDD I = input O = output P = Power L = LCD Driver
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 7
PIC16C712/716
NOTES:
DS41106A-page 8
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
2.0 MEMORY ORGANIZATION
FIGURE 2-2:
There are two memory blocks in each of these PICmicro(R) microcontroller devices. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur. Additional information on device memory may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023).
PROGRAM MEMORY MAP AND STACK OF PIC16C716
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
2.1
Program Memory Organization
Stack Level 8 Reset Vector
The PIC16C712/716 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. PIC16C712 has 1K x 14 words of program memory and PIC16C716 has 2K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wraparound. User Memory Space The reset vector is at 0000h and the interrupt vector is at 0004h.
0000h
Interrupt Vector
0004h 0005h
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK OF THE PIC16C712
PC<12:0>
On-chip Program Memory 07FFh 0800h
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
1FFFh
Stack Level 8 Reset Vector
0000h
User Memory Space
Interrupt Vector
0004h 0005h
On-chip Program Memory 03FFh 0400h
1FFFh
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 9
PIC16C712/716
2.2 Data Memory Organization FIGURE 2-3:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Registers 96 Bytes 7Fh Bank 0 Bank 1 ADRES ADCON0 ADCON1 General Purpose Registers 32 Bytes CCPR1L CCPR1H CCP1CON TMR1L TRM1H T1CON TRM2 T2CON PR2 PCON PCLATH INTCON PIR1 PCLATH INTCON PIE1 INDF(1) TMR0 PCL STATUS FSR PORTA PORTB DATACCP INDF(1)
OPTION_REG
REGISTER FILE MAP
File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BFh C0h FFh
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1(1) = 00 = 01 = 10 = 11 RP0 (STATUS<6:5>)
PCL STATUS FSR TRISA TRISB TRISCCP
Bank0 Bank1 Bank2 (not implemented) Bank3 (not implemented)
Note 1: Maintain this bit clear to ensure upward compatibility with future products.
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some "high use" special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 2.5).
Unimplemented data memory locations, read as '0'. Note 1: Not a physical register.
DS41106A-page 10
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1. The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.
TABLE 2-1
Addr Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (4)
Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h-09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h-14h 15h 16h 17h 18h-1Dh 1Eh 1Fh CCPR1L CCPR1H CCP1CON -- ADRES ADCON0 Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- Unimplemented A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 -- -- INDF(1) TMR0 PCL(1) STATUS FSR(1) PORTA
(5,6) (1)
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO PD Z DC C
0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 rr01 1xxx rr0q quuu xxxx xxxx uuuu uuuu --xx xxxx --xu uuuu xxxx xxxx uuuu uuuu
Indirect data memory address pointer -- -- --
(7)
PORTA Data Latch when written: PORTA pins when read
PORTB(5,6) DATACCP -- PCLATH
(1,2)
PORTB Data Latch when written: PORTB pins when read --(7) Unimplemented -- GIE -- -- PEIE ADIF -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- T0IF CCP1IF INTF TMR2IF RBIF TMR1IF --(7) --(7) --(7) --(7) DCCP --
(7)
DT1CK
xxxx xxxx xxxx xuxu -- --
---0 0000 ---0 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000 -- --
INTCON(1) PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON
Unimplemented Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --uu uuuu 0000 0000 0000 0000
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000
xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved. Always maintain these bits clear. 5: On any device reset, these pins are configured as inputs. 6: This is the value that will be in the port output latch. 7: Reserved bits; Do Not Use.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 11
PIC16C712/716
TABLE 2-1
Addr Name
SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (4)
Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h-89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-91h 92h 93h-9Eh 9Fh PR2 -- ADCON1 INDF(1) OPTION_ REG PCL
(1) (1)
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte IRP
(4)
STATUS FSR(1) TRISA TRISB
RP1
(4)
RP0
TO
PD
Z
DC
C
rr01 1xxx rr0q quuu xxxx xxxx uuuu uuuu --x1 1111 --x1 1111 1111 1111 1111 1111
Indirect data memory address pointer -- -- --
(7)
PORTA Data Direction Register
PORTB Data Direction Register --
(7)
TRISCCP -- PCLATH
(1,2)
--(7)
--(7)
--(7)
--(7)
TCCP
--(7)
TT1CK
xxxx x1x1 xxxx x1x1 -- --
Unimplemented -- GIE -- -- PEIE ADIE -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- T0IF CCP1IE INTF TMR2IE RBIF TMR1IE
---0 0000 ---0 0000 0000 000x 0000 000u -0-- -000 -0-- -000 -- --
INTCON(1) PIE1 -- PCON --
Unimplemented -- Unimplemented Timer2 Period Register Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0 -- -- -- -- -- POR BOR
---- --qq ---- --uu -- --
1111 1111 1111 1111 -- ---- -000 -- ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved. Always maintain these bits clear. 5: On any device reset, these pins are configured as inputs. 6: This is the value that will be in the port output latch. 7: Reserved bits; Do Not Use.
DS41106A-page 12
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
2.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 2-4, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." Note 1: These devices do not use bits IRP and RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
FIGURE 2-4:
R/W-0 IRP bit7
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0
R/W-0 RP1
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear 0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes Note: RP1 = not implemented, maintain clear bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 13
PIC16C712/716
2.2.2.2 OPTION_REG REGISTER Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB.
FIGURE 2-5:
R/W-1 RBPU bit7
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
R/W-1 INTEDG
bit 7:
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
DS41106A-page 14
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
FIGURE 2-6:
R/W-0 GIE bit7
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
R/W-0 PEIE
bit 7:
GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt IINTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 15
PIC16C712/716
2.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
FIGURE 2-7:
U-0
--
PIE1 REGISTER (ADDRESS 8Ch)
U-0
--
R/W-0 ADIE
U-0
--
R/W-0
--
R/W-0 CCP1IE
R/W-0 TMR2IE
R/W-0 TMR1IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit7
bit 7: bit 6:
Unimplemented: Read as `0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 5-3: Unimplemented: Read as `0' bit 2:
bit 1:
bit 0:
DS41106A-page 16
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
FIGURE 2-8:
U-0
--
PIR1 REGISTER (ADDRESS 0Ch)
U-0
--
R/W-0 ADIF
U-0
--
R/W-0
--
R/W-0 CCP1IF
R/W-0 TMR2IF
R/W-0 TMR1IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit7
bit 7: bit 6:
Unimplemented: Read as `0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 5-3: Unimplemented: Read as `0' bit 2:
bit 1:
bit 0:
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 17
PIC16C712/716
2.2.2.6 PCON REGISTER Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. These devices contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. If the BODEN configuration bit is set, BOR is '1' on Power-on Reset. If the BODEN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BODEN configuration bit is clear). BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred.
FIGURE 2-9:
U-0 -- bit7
PCON REGISTER (ADDRESS 8Eh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-q BOR bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0:
DS41106A-page 18
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
2.3 PCL and PCLATH 2.4 Program Memory Paging
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.1 STACK The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper bit of the address is provided by PCLATH<3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bit is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the return instructions (which POPs the address from the stack).
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 19
PIC16C712/716
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
EXAMPLE 2-2:
HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
EXAMPLE 2-1:
* * * *
INDIRECT ADDRESSING
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 06) * A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).
NEXT
movlw movwf clrf incf btfss goto :
CONTINUE
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-10. However, IRP is not used in the PIC16C712/716.
FIGURE 2-10: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0 6 from opcode 0 IRP
Indirect Addressing
7 FSR register 0
(2)
bank select location select 00 00h 01 80h 10 100h 11 180h
(2)
bank select location select
Data Memory(1)
(3)
(3)
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register file map detail see Figure 2-3. 2: Maintain clear for upward compatibility with future products. 3: Not implemented.
DS41106A-page 20
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual, (DS33023). Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. PORTA pins, RA3:0, are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
3.1
PORTA and the TRISA Register
PORTA is a 5-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, the value is modified, and then written to the port data latch.
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<4> as outputs Return to Bank 0
STATUS, RP0 PORTA
BSF MOVLW
STATUS, RP0 0xEF
MOVWF BCF
TRISA STATUS, RP0
FIGURE 3-1:
BLOCK DIAGRAM OF RA3:RA0
DATA BUS WR PORT
D
Q VDD VDD
CK
Q
P
Data Latch D WR TRIS Q N I/O pin
CK
Q
TRIS Latch
VSS VSS Analog input mode
RD TRIS Q D
TTL Input Buffer
EN RD PORT
To A/D Converter
(c) 1998 Microchip Technology Inc.
Preliminary
DS41106A-page 21
PIC16C712/716
FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
DATA BUS WR PORT
D Q Q
CK
N Data Latch
D Q Q
I/O Pin
VSS
VSS
WR TRIS
CK
TRIS Latch
Schmitt Trigger Input Buffer
RD TRIS
Q D EN EN
RD PORT TMR0 Clock Input
TABLE 3-1
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 Buffer TTL TTL TTL TTL Function Input/output or analog input Input/output or analog input Input/output or analog input
Input/output or analog input or VREF Input/output or external clock input for Timer0 RA4/T0CKI bit4 ST Output is open drain type Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2
Address 05h 85h 9Fh
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 -- -- -- -- -- -- --(1) --(1) -- RA4 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR --xx xxxx --11 1111 ---- -000 Value on all other resets --xu uuuu --11 1111 ---- -000
Name PORTA TRISA ADCON1
PORTA Data Direction Register -- -- PCFG2 PCFG1 PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: Reserved bits; Do Not Use.
DS41106A-page 22
Preliminary
(c) 1998 Microchip Technology Inc.
PIC16C712/716
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
EXAMPLE 3-1:
BCF CLRF
INITIALIZING PORTB
; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
STATUS, RP0 PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
FIGURE 3-3:
BLOCK DIAGRAM OF RB0 PIN
VDD RBPU(1) Data Latch D Q CK TRIS Latch D Q WR TRIS CK I/O pin VSS weak VDD P pull-up
DATA BUS WR PORT
TTL Input Buffer
RD TRIS Q RD PORT D EN
RB0/INT Schmitt Trigger Buffer Note 1: RD PORT
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 23
PIC16C712/716
PORTB pins RB3:RB1 are multiplexed with several peripheral functions (Table 3-3). PORTB pins RB3:RB0 have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTB pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISB as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins, RB7:RB4, are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.
FIGURE 3-4:
BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
RBPU(1) T1OSCEN T1CS DATA BUS RD DATACCP DATACCP<0> D WR DATACCP CK Q Q VDD weak P pull-up VDD
TRISCCP<0> D WR TRISCCP CK Q Q
1
RB1/T1OSO/T1CKI
0
PORTB<1> D WR PORTB CK Q Q
1
VSS
0
TRISB<1> D WR TRISB T1OSCEN TMR1CS CK Q Q
1
TTL Buffer RD PORTB
0
T1CLKIN ST Buffer
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS41106A-page 24
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN
VDD RBPU(1) T1OSCEN PORTB<2> DATA BUS WR PORTB D CK Q Q RB1/T1OSO/T1CKI weak P pull-up VDD
TRISB<2> D WR TRISB CK Q Q
VSS
T1OSCEN
RD PORTB
TTL Buffer
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 3-6:
BLOCK DIAGRAM OF RB3/CCP1 PIN
RBPU(1) CCPON
DATA BUS RD DATACCP
1
CCPON DATACCP<2> D Q Q
CCPIN CCPOUT
0
1 0
VDD weak P pull-up VDD
WR DATACCP
CK
TRISCCP<2> D WR TRISCCP CCP Output Mode PORTB<3> D WR PORTB CK Q Q CK Q Q
1
RB3/CCP1
0
1 0
VSS
TRISB<3> D WR TRISB CCPON CK Q Q
1
RD PORTB
0
TTL Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 25
PIC16C712/716
FIGURE 3-7: BLOCK DIAGRAM OF RB7:RB4 PINS
VDD RBPU(1) Data Latch D Q CK TRIS Latch D Q WR TRIS CK TTL Buffer ST Buffer RD TRIS Q RD PORT Set RBIF I/O pin weak P pull-up VDD
DATA BUS WR PORT
VSS
Latch D EN Q1
From other RB7:RB4 pins
Q
D RD PORT EN Q3
RB7:RB6 in serial programming mode Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
TABLE 3-3
Name RB0/INT
PORTB FUNCTIONS
Bit# bit0 Buffer TTL/ST(1) Function
Input/output pin or external interrupt input. Internal software programmable weak pull-up. (1) Input/output pin or Timer 1 oscillator output, or Timer 1 clock input. Internal RB1/T1OS0/ bit1 TTL/ST software programmable weak pull-up. See Timer1 section for detailed T1CKI operation. (1) RB2/T1OSI bit2 Input/output pin or Timer 1 oscillator input. Internal software programmable TTL/ST weak pull-up. See Timer1 section for detailed operation. (1) RB3/CCP1 bit3 Input/output pin or Capture 1 input, or Compare 1 output, or PWM1 output. TTL/ST Internal software programmable weak pull-up. See CCP1 section for detailed operation. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Input/output pin (with interrupt on change). Internal software programmable RB6 bit6 TTL/ST(2) weak pull-up. Serial programming clock. Input/output pin (with interrupt on change). Internal software programmable RB7 bit7 TTL/ST(2) weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
DS41106A-page 26
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
TABLE 3-4
Address 06h 86h 81h Name PORTB TRISB OPTION_REG
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on: POR, BOR xxxx xxxx 1111 1111 PSA PS2 PS1 PS0 1111 1111 Value on all other resets uuuu uuuu 1111 1111 1111 1111
PORTB Data Direction Register RBPU INTEDG T0CS T0SE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 27
PIC16C712/716
NOTES:
DS41106A-page 28
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h Additional information on external clock requirements is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
4.2
Prescaler
Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available, which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer and vice-versa. The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Data Bus FOSC/4 0 1 1 Programmable Prescaler(2) 3 T0CS(1) PS2, PS1, PS0(1) PSA(1) Set interrupt flag bit T0IF on overflow PSout Sync with Internal clocks (2 cycle delay) TMR0 PSout 8
RA4/T0CKI pin T0SE(1)
0
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 29
PIC16C712/716
4.2.1 SWITCHING PRESCALER ASSIGNMENT
4.3
Timer0 Interrupt
The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicroTM Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 reg
CLKOUT (=Fosc/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA
Set flag bit T0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1
Address 01h 0Bh,8Bh 81h 85h
REGISTERS ASSOCIATED WITH TIMER0
Name TMR0 INTCON OPTION_REG TRISA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR xxxx xxxx INTE T0SE Bit 4 RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 --11 1111 Value on all other resets uuuu uuuu 0000 000u 1111 1111 --11 1111
Timer0 module's register GIE PEIE T0IE T0CS --(1)
RBPU INTEDG -- --
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Note 1: Reserved bit; Do Not Use.
DS41106A-page 30
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
5.0 TIMER1 MODULE
5.1 Timer1 Operation
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) * Readable and writable (Both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * Reset from CCP module trigger Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Figure 5-2 is a simplified block diagram of the Timer1 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023). Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RB2/T1OSI and RB1/T1OSO/T1CKI pins become inputs. That is, the TRISB<2:1> value is ignored. Timer1 also has an internal "reset input". This reset can be generated by the CCP module (Section 7.0).
FIGURE 5-1:
U-0 -- bit7
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 T1SYNC R/W-0 R/W-0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
T1CKPS1 T1CKPS0 T1OSCEN
TMR1CS TMR1ON
bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB1/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 2:
bit 0:
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 31
PIC16C712/716
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
Set flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON on/off T1SYNC
Synchronized clock input
T1OSC RB1/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Synchronize det
RB2/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
5.2
Timer1 Module and PORTB Operation
When Timer1 is configured as timer running from the main oscillator, PORTB<2:1> operate as normal I/O lines. When Timer1 is configured to function as a counter however, the clock source selection may affect the operation of PORTB<2:1>. Multiplexing details of the Timer1 clock selection on PORTB are shown in Figure 3-4 and Figure 3-5. The clock source for Timer1 in the counter mode can be from one of the following: 1. 2. 3. External circuit connected to the RB1/T1OSO/T1CKI pin Firmware controlled DATACCP<0> bit, DT1CKI Timer1 oscillator
Table 5-1 shows the details of Timer1 mode selections, control bit settings, TMR1 and PORTB operations.
DS41106A-page 32
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
TABLE 5-1
TMR1 Module Mode Off Timer
TMR1 MODULE AND PORTB OPERATION
Control Bits T1CON = --xx 0x00 T1CON = --xx 0x01 Off TMR1 module uses the main oscillator as clock source. TMR1ON can turn on or turn off Timer1. TMR1 module uses the external signal on the RB1/T1OSO/T1CKI pin as a clock source. TMR1ON can turn on or turn off Timer1. DT1CK can read the signal on the RB1/T1OSO/T1CKI pin. DATACCP<0> bit drives RB1/T1OSO/T1CKI and produces the TMR1 clock source. TMR1ON can turn on or turn off Timer1. The DATACCP<0> bit, DT1CK, can read and write to the RB1/T1OSO/T1CKI pin. RB1/T1OSO/T1CKI and RB2/T1OSI are configured as a 2 pin crystal oscillator. RB1/T1OSI/T1CKI is the clock input for TMR1. TMR1ON can turn on or turn off Timer1. DATACCP<1> bit, DT1CK, always reads 0 as input and can not write to the RB1/T1OSO/T1CK1 pin. TMR1 Module Operation PORTB<2:1> Operation PORTB<2:1> function as normal I/O PORTB<2:1> function as normal I/O
Clock Source N/A Fosc/4
External circuit
T1CON = --xx 0x11 TR1SCCP = ---- -x-1
Firmware
T1CON = --xx 0x11 TR1SCCP = ---- -x-0
PORTB<2> functions as normal I/O. PORTB<1> always reads 0 when configured as input . If PORTB<1> is configured as output, reading PORTB<1> will read the data latch. Writing to PORTB<1> will always store the result in the data latch, but not to the RB1/T1OSO/T1CKI pin. If the TMR1CS bit is cleared (TMR1 reverts to the timer mode), then pin PORTB<1> will be driven with the value in the data latch. PORTB<2:1> always read 0 when configured as inputs. If PORTB<2:1> are configured as outputs, reading PORTB<2:1> will read the data latches. Writing to PORTB<2:1> will always store the result in the data latches, but not to the RB2/T1OSI and RB1/T1OSO/T1CKI pins. If the TMR1CS and T1OSCEN bits are cleared (TMR1 reverts to the timer mode and TMR1 oscillator is disabled), then pin PORTB<2:1> will be driven with the value in the data latches.
Counter Timer1 oscillator T1CON = --xx 1x11
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 33
PIC16C712/716
5.3 Timer1 Oscillator 5.4 Timer1 Interrupt
A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-2 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.5
Resetting Timer1 using a CCP Trigger Output
TABLE 5-2
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq 32 kHz 100 kHz 200 kHz C1 33 pF 15 pF 15 pF C2 33 pF 15 pF 15 pF
If the CCP module is configured in compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
These values are for design guidance only.
Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.
TABLE 5-3
Address Name 0Bh,8Bh 0Ch 8Ch 0Eh 0Fh 10h 07h 87h Legend:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 Bit 6 GIE -- -- PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE -- -- Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR, BOR Value on all other resets
INTCON PIR1 PIE1 TMR1L TMR1H T1CON DATACCP TRISCCP
0000 000x 0000 000u -0-- -000 -0-- -000 -0-- -000 -0-- -000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register -- -- -- -- -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu -- -- -- -- -- -- DCCP TCCP -- -- DT1CK TT1CK ---- -x-x ---- -u-u ---- -1-1 ---- -1-1
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
DS41106A-page 34
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
NOTES:
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 35
PIC16C712/716
6.0
* * * * * *
TIMER2 MODULE
The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (Both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2
Timer2 has a control register, shown in Figure 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 6-2 is a simplified block diagram of the Timer2 module. Additional information on timer modules is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
FIGURE 6-1:
U-0 -- bit7
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
T2CKPS1 T2CKPS0
bit 7: bit 6-3:
Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale 0011 = 1:4 Postscale 0100 = 1:5 Postscale 0101 = 1:6 Postscale 0110 = 1:7 Postscale 0111 = 1:8 Postscale 1000 = 1:9 Postscale 1001 = 1:10 Postscale 1010 = 1:11 Postscale 1011 = 1:12 Postscale 1100 = 1:13 Postscale 1101 = 1:14 Postscale 1110 = 1:15 Postscale 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2:
bit 1-0:
FIGURE 6-2:
Sets flag bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2 output Reset Prescaler 1:1, 1:4, 1:16 2
TMR2 reg Comparator
FOSC/4
Postscaler 1:1 to 1:16 4
EQ
PR2 reg
DS41106A-page 36
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
6.1 Timer2 Operation 6.2 Timer2 Interrupt
Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset.
TABLE 6-1
Address 0Bh,8Bh 0Ch 8Ch 11h 12h 92h Legend: Name INTCON PIR1 PIE1 TMR2 T2CON PR2
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE Bit 2 T0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR, BOR Value on all other resets
0000 000x 0000 000u -00- -000 0000 -000 -0-- -000 0000 -000 0000 0000 0000 0000
-- --
Timer2 module's register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 37
PIC16C712/716
NOTES:
DS41106A-page 38
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
7.0 CAPTURE/COMPARE/PWM (CCP) MODULE(S)
Additional information on the CCP module is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
Each CCP (Capture/Compare/PWM) module contains a 16-bit register, which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes. Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.
TABLE 7-1
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
FIGURE 7-1:
U-0 -- bit7 U-0 --
CCP1CON REGISTER (ADDRESS 17h)
R/W-0 DC1B1 R/W-0 R/W-0 DC1B0 CCP1M3 R/W-0 CCP1M2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-6: Unimplemented: Read as '0' bit 5-4: DC1B1:DC1B0: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode
FIGURE 7-2:
R/W-1 -- bit7
TRISCCP Register (ADDRESS 87h)
R/W-1 -- R/W-1 -- R/W-1 -- R/W-1 TCCP R/W-1 -- R/W-1 TT1CK bit0
R/W-1 --
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset
bit 7-3: bit 2:
Reserved bits; Do Not Use TCCP - Tri state control bit for CCP 0 = Output pin driven 1 = Output pin tristated Reserved bit; Do Not Use TT1CK - Tri state control bit for T1CKI pin 0 = T1CKI pin is an output 1 = T1CKI pin is an input
bit 1: bit 0:
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 39
PIC16C712/716
7.1 Capture Mode
7.1.4 CCP PRESCALER In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost.
EXAMPLE 7-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value
FIGURE 7-3:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set flag bit CCP1IF (PIR1<2>)
CCP1CON NEW_CAPT_PS
Prescaler / 1, 4, 16 RB3/CCP1 Pin and edge detect
MOVWF
CCPR1L
CCP1CON
CCPR1H Capture Enable TMR1H CCP1CON<3:0> Q's
TMR1L
7.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCP output must be disabled by setting the TRISCCP<2> bit. Note: If the RB3/CCP1 is configured as an output by clearing the TRISCCP<2> bit, a write to the DCCP bit can cause a capture condition. TIMER1 MODE SELECTION
7.1.2
Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 7.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.
DS41106A-page 40
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
7.2 Compare Mode
7.2.1 CCP PIN CONFIGURATION In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RB3/CCP1 pin is either: * driven High * driven Low * remains Unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. The user must configure the RB3/CCP1 pin as the CCP output by clearing the TRISCCP<2> bit. Note: Clearing the CCP1CON register will force the RB3/CCP1 compare output latch to the default low level. This is neither the PORTB I/O data latch nor the DATACCP latch. TIMER1 MODE SELECTION
7.2.2
FIGURE 7-4:
COMPARE MODE OPERATION BLOCK DIAGRAM
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 7.2.3 SOFTWARE INTERRUPT MODE
Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion Special Event Trigger Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S Output Logic match RB3/CCP1 R Pin TRISCCP<2> Output Enable CCP1CON<3:0> Mode Select Comparator TMR1H TMR1L
When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). 7.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger output of CCP1 also starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
TABLE 7-2
Address
07h 0Bh,8Bh 0Ch 0Eh 0Fh 10h 15h 16h 17h 87h 8Ch
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7
-- GIE --
Name
DATACCP INTCON PIR1 TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON TRISCCP PIE1
Bit 6
-- PEIE ADIF
Bit 5
-- T0IE --
Bit 4
-- INTE --
Bit 3
-- RBIE --
Bit 2
DCCP T0IF CCP1IF
Bit 1
-- INTF TMR2IF
Bit 0
TT1CK RBIF
Value on POR, BOR
Value on all other resets
xxxx xxxx xxxx xuxu 0000 000x 0000 000u
TMR1IF -0-- -000 -0-- -000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 TCCP CCP1IE -- TMR2IE TT1CK xxxx x1x1 xxxx x1x1
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- -- -- -- ADIE DC1B1 -- -- DC1B0 -- -- CCP1M3 -- --
TMR1IE -0-- -000 -0-- -000
Legend:
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 41
PIC16C712/716
7.3 PWM Mode
7.3.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISCCP<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is neither the PORTB I/O data latch nor the DATACCP latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 6.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE
Figure 7-5 shows a simplified block diagram of the CCP module in PWM mode. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3.
FIGURE 7-5:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty cycle registers CCPR1L
7.3.2
CCPR1H (Slave)
Comparator
R
Q RB3/CCP1
TMR2
(Note 1) S TRISCCP<2> Clear Timer, CCP1 pin and latch D.C.
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * Tosc * (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: FOSC log( FPWM log(2)
Comparator
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 7-6) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 7-6:
PWM OUTPUT
Period = PR2+1
Duty Cycle TMR2 = PR2 Note: TMR2 = Duty Cycle (CCPR1H) TMR2 = PR2
=
)
bits
If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared.
For an example PWM period and duty cycle calculation, see the PICmicroTM Mid-Range Reference Manual, (DS33023).
DS41106A-page 42
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISCCP<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
TABLE 7-3
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 5.5
Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 7-4
Address Name
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 -- GIE -- Bit 6 -- PEIE ADIF Bit 5 -- T0IE -- Bit 4 -- INTE -- Bit 3 -- RBIE -- Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets
07h
0Bh,8Bh 0Ch 11h 12h 15h 16h 17h
DATACCP
INTCON PIR1 TMR2 T2CON CCPR1L CCPR1H CCP1CON
DCCP
T0IF CCP1IF
--
INTF TMR2IF
DT1CK
RBIF TMR1IF
xxxx xxxx xxxx xuxu
0000 000x 0000 000u -0-- -000 -0-- -000 0000 0000 0000 0000
Timer2 module's register --
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 -- --
Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- -- -- -- ADIE DC1B1 -- -- DC1B0 -- --
87h
8Ch 92h Legend:
TRISCCP
PIE1 PR2
TCCP
CCP1IE
-- TMR2IE
TT1CK
TMR1IE
xxxx x1x1 xxxx x1x1
-0-- -000 -0-- -000 1111 1111 1111 1111
Timer2 module's period register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 43
PIC16C712/716
7.4 CCP1 Module and PORTB Operation
When the CCP module is disabled, PORTB<3> operates as a normal I/O pin. When the CCP module is enabled, PORTB<3> operation is affected. Multiplexing details of the CCP1 module are shown on PORTB<3>, refer to Figure 3.6. Table 7-5 below shows the effects of the CCP module operation on PORTB<3> .
TABLE 7-5
CCP1 Module Mode Off Capture
CCP1 MODULE AND PORTB OPERATION
Control Bits CCP1 Module Operation PORTB<3> Operation PORTB<3> functions as normal I/O. PORTB<3> always reads 0 when configured as input. If PORTB<3> is configured as output, reading PORTB<3> will read the data latch. Writing to PORTB<3> will always store the result in the data latch, but it does not drive the RB3/CCP1 pin.
Compare
PWM
CCP1CON = --xx 0000 Off CCP1CON = --xx 01xx The CCP1 module will capture an event TR1SCCP = ---- -1-x on the RB3/CCP1 pin which is driven by an external circuit. The DCCP bit can read the signal on the RB3/CCP1 pin. CCP1CON = --xx 01xx The CCP1 module will capture an event TR1SCCP = ---- -0-x on the RB3/CCP1 pin which is driven by the DCCP bit. The DCCP bit can read the signal on the RB3/CCP1 pin. CCP1CON = --xx 10xx The CCP1 module produces an output TR1SCCP = ---- -0-x on the RB3/CCP1 pin when a compare event occurs. The DCCP bit can read the signal on the RB3/CCP1 pin. CCP1CON = --xx 11xx The CCP1 module produces the PWM TR1SCCP = ---- -0-x signal on the RB3/CCP1 pin. The DCCP bit can read the signal on the RB3/CCP1 pin.
DS41106A-page 44
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
8.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
Additional information on the A/D module is available in the PICmicroTM Mid-Range Reference Manual, (DS33023). The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1) A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The ADCON0 register, shown in Figure 8-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 8-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.
The analog-to-digital (A/D) converter module has four inputs. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator.
FIGURE 8-1:
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit0
R/W-0 R/W-0 ADCS1 ADCS0 bit7
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal ADC RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 1xx = reserved, do not use bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: bit 0: Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 45
PIC16C712/716
FIGURE 8-2:
U-0 -- bit7
ADCON1 REGISTER (ADDRESS 9Fh)
U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0
U-0 --
R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset
bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 0x0 0x1 100 101 11x A = Analog input D = Digital I/O RA0 A A A A D RA1 A A A A D RA2 A A D D D RA3 A VREF A VREF D VREF VDD RA3 VDD RA3 VDD
DS41106A-page 46
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 8-3. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 8.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins/voltage reference/ and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For the next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
2.
3. 4. 5.
FIGURE 8-3:
A/D BLOCK DIAGRAM
CHS2:CHS0 VIN (Input voltage) 011 010 A/D Converter 001 RA1/AN1 VDD VREF (Reference voltage) PCFG2:PCFG0 000 or 010 or 100 or 110 or 111 001 or 011 or 101 000 RA0/AN0 RA2/AN2 RA3/AN3/VREF
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 47
PIC16C712/716
8.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, TACQ, see the PICmicroTM Mid-Range Reference Manual, (DS33023). This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. Note: When the conversion is started, the holding capacitor is disconnected from the input pin.
FIGURE 8-4:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
Rs
ANx
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
DS41106A-page 48
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
8.2 Selecting the A/D Conversion Clock 8.3 Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal RC oscillator The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN3:AN0 pins), may cause the input buffer to consume current that is out of the devices specification.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 8-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 8-1
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency 20 MHz 100 ns(2) 400 ns(2) 1.6 s 5 MHz 400 1.6 s 6.4 s ns(2) 1.25 MHz 1.6 s 6.4 s 25.6 s(3) 333.33 kHz 6 s 24 s(3) 96 s(3)
AD Clock Source (TAD) Operation 2TOSC 8TOSC 32TOSC RC(5) Legend: Note 1: 2: 3: 4: ADCS1:ADCS0 00 01 10 11
2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1) 2 - 6 s(1,4) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 49
PIC16C712/716
8.4
Note:
A/D Conversions
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
8.5
Use of the CCP Trigger
An A/D conversion can be started by the "special event trigger" of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter.
TABLE 8-2
Address 05h 0Bh,8Bh 0Ch 1Eh 1Fh 85h 8Ch 9Fh Name
SUMMARY OF A/D REGISTERS
Bit 7 -- GIE -- ADCS1 -- -- -- Bit 6 -- PEIE ADIF Bit 5 --(1) T0IE -- Bit 4 RA4 INTE -- Bit 3 RA3 RBIE -- Bit 2 RA2 T0IF CCP1IF Bit 1 RA1 INTF TMR2IF Bit 0 RA0 RBIF Value on POR, BOR --xx xxxx 0000 000x Value on all other Resets --xu uuuu 0000 000u -0-- -000 uuuu uuuu 0000 00-0 ---1 1111 -0-- 0000 ---- -000
PORTA INTCON PIR1 ADRES ADCON0 TRISA PIE1 ADCON1
TMR1IF -0-- -000 xxxx xxxx
A/D Result Register ADCS0 -- ADIE -- CHS2 --(1) -- -- CHS1 CHS0 GO/DONE -- ADON
0000 00-0 ---1 1111
PORTA Data Direction Register -- -- -- -- CCP1IE PCFG2 PCFG1 PCFG0
TMR2IE TMR1IE -0-- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Reserved bits; Do Not Use.
DS41106A-page 50
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
9.0 SPECIAL FEATURES OF THE CPU
the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options. Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
The PIC16C712/716 devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * OSC Selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-Circuit Serial ProgrammingTM (ICSP) These devices have a Watchdog Timer, which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only and is designed to keep
9.1
Configuration Bits
The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 51
PIC16C712/716
FIGURE 9-1:
CP1 bit13 CP0
CONFIGURATION WORD
CP1 CP0 CP1 CP0 -- BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit0
Register:CONFIG Address2007h
bit 13-8, 5-4: CP1:CP0: Code Protection bits (2) Code Protection for 2K Program memory (PIC16C716) 11 = Programming code protection off 10 = 0400h - 07FFh code protected 01 = 0200h - 07FFh code protected 00 = 0000h - 07FFh code protected bit 13-8, 5-4: Code Protection for 1K Program memory (PIC16C712) 11 = Programming code protection off 10 = Programming code protection off 01 = 0200h - 03FFh code protected 00 = 0000h - 03FFh code protected bit 7: bit 6: Unimplemented: Read as '1' BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator
bit 3:
bit 2:
bit 1-0:
Note 1:Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2:All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS41106A-page 52
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
9.2
9.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 9-1
Ranges Tested: Mode XT
CERAMIC RESONATORS
The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR/CERAMIC RESONATORS
Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz
OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
HS
These values are for design guidance only. See notes at bottom of page.
9.2.2
TABLE 9-2
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 9-2). The PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 9-3).
Osc Type LP XT
HS
4 MHz 8 MHz 20 MHz
FIGURE 9-2:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To internal logic SLEEP
These values are for design guidance only. See notes at bottom of page.
C1(1)
XTAL OSC2 C2(1) RS(2)
RF(3)
PIC16C7XX
Note 1: See Table 9-1 and Table 9-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen.
Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 9-1). 2: Higher capacitance increases the stability of the oscillator, but also increases the startup time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode, as well as XT mode to avoid overdriving crystals with low drive level specification.
FIGURE 9-3:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1
Clock from ext. system Open
PIC16C7XX
OSC2
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 53
PIC16C712/716
9.2.3 RC OSCILLATOR
9.3
Reset
For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-4 shows how the R/C combination is connected to the PIC16CXXX.
The PIC16CXXX differentiates between various kinds of reset: * * * * * * Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR)
FIGURE 9-4:
VDD Rext
RC OSCILLATOR MODE
OSC1 Cext VSS Fosc/4 Recommended values: OSC2/CLKOUT
Internal clock
Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 9-4. These bits are used in software to determine the nature of the reset. See Table 9-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 9-6. The PICmicro microcontrollers have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low.
PIC16C7XX
3 k Rext 100 k Cext > 20pF
DS41106A-page 54
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
9.4 Power-On Reset (POR) 9.5 Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (to a level of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified (parameter D004). For a slow rise time, see Figure 9-5. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. The Power-up Timer provides a fixed nominal time-out (parameter #33), on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details.
9.6
Oscillator Start-up Timer (OST)
FIGURE 9-5:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD VDD R R1 MCLR C PIC16C7XX
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #32). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
9.7
Brown-Out Reset (BOD)
Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
The PIC16C712/716 members have on-chip Brown-out Reset circuitry. A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V, refer to VBOR parameter D005(VBOR) for a time greater than parameter (TBOR) in Table 12-6. The brown-out situation will reset the chip. A reset is not guaranteed to occur if VDD falls below 4.0V for less than parameter (TBOR). On any reset (Power-on, Brown-out, Watchdog, etc.) the chip will remain in Reset until VDD rises above VBOR. The Power-up Timer will now be invoked and will keep the chip in reset an additional 72 ms. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-Up Timer will execute a 72 ms reset. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 9-7 shows typical Brown-out situations. For operations where the desired brown-out voltage is other than 4V, an external brown-out circuit must be used. Figure 9-8, 9-9 and 9-10 show examples of external brown-out protection circuits.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 55
PIC16C712/716
FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset MCLR WDT Module VDD rise detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter R Q Chip_Reset Power-on Reset S SLEEP WDT Time-out Reset
BODEN
PWRT Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
See Table 9-3 for time-out BODEN situations.
FIGURE 9-7:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal Reset VDD
72 ms
VBOR
Internal Reset
<72 ms
72 ms
VDD
VBOR
Internal Reset
72 ms
DS41106A-page 56
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 9-8:
VDD 33k Q1 10k 40k MCLR
PIC16C7XX Vss VDD RST
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD
FIGURE 9-10: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3
VDD MCP809
bypass capacitor
VDD
MCLR
PIC16C7XX
Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit.
This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both high and low active reset pins. There are 7 different trip point selections to accommodate 5V and 3V systems
9.8 FIGURE 9-9:
VDD R1 Q1 MCLR R2 40k
PIC16C7XX
Time-out Sequence
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
VDD
On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 9-11, Figure 9-12, and Figure 9-13 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 9-13). This is useful for testing purposes or to synchronize more than one PIC16CXXX device operating in parallel. Table 9-5 shows the reset conditions for some special function registers, while Table 9-6 shows the reset conditions for all the registers.
Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that:
R1 VDD x R1 + R2 = 0.7 V
9.9
2: Internal brown-out reset should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
Power Control/Status Register (PCON)
The Power Control/Status Register, PCON has two bits. Bit0 is Brown-out Reset Status bit, BOR. If the BODEN configuration bit is set, BOR is '1' on Power-on Reset. If the BODEN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BODEN configuration bit is clear). BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 57
PIC16C712/716
TABLE 9-3 TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 72 ms + 1024TOSC 72 ms PWRTE = 1 1024TOSC -- Brown-out 72 ms + 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC -- Oscillator Configuration XT, HS, LP RC
TABLE 9-4
POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 9-5
RESET CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
DS41106A-page 58
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
TABLE 9-6
Register W INDF TMR0 PCL STATUS FSR PORTA(4) PORTB(5) DATACCP PCLATH INTCON PIR1 -0-- 0000 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON ADRES ADCON0 OPTION_REG TRISA TRISB TRISCCP PIE1 PCON PR2 ADCON1
Legend: Note 1: 2: 3: 4: 5:
INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16C712/716
Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx ---- -x-x ---0 0000 0000 -00x ---- 0000 MCLR Resets WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q quuu(3) uuuu uuuu --xx xxxx uuuu uuuu ---- -u-u ---0 0000 0000 -00u ---- 0000 -0-- 0000 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0 1111 1111 --11 1111 1111 1111 xxxx x1x1 ---- 0000 -0-- 0000 ---- --uq 1111 1111 ---- -000 Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu --xu uuuu uuuu uuuu ---- -u-u ---u uuuu uuuu -uuu(1) ---- uuuu(1) -u-- uuuu(1) uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uu-u uuuu uuuu --uu uuuu uuuu uuuu xxxx xuxu ---- uuuu -u-- uuuu ---- --uq 1111 1111 ---- -uuu
xxxx xxxx xxxx xxxx --00 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 00-0 1111 1111 --11 1111 1111 1111 xxxx x1x1 ---- 0000 -0-- 0000 ---- --0q 1111 1111 ---- -000
u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 9-5 for reset value for specific condition. On any device reset, these pins are configured as inputs. This is the value that will be in the port output latch.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 59
PIC16C712/716
FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS41106A-page 60
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
9.10 Interrupts
The PIC16C712/716 devices have up to 7 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register, INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.
FIGURE 9-14: INTERRUPT LOGIC
Wake-up (If in SLEEP mode)
T0IF T0IE INTF INTE ADIF ADIE RBIF RBIE PEIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE GIE
Interrupt to CPU
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 61
PIC16C712/716
9.10.1 INT INTERRUPT
9.11
Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered, either rising if bit INTEDG (OPTION_REG<6>) is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.13 for details on SLEEP mode. 9.10.2 TMR0 INTERRUPT
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. Example 9-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The example: a) b) c) d) e) f) Stores the W register. Stores the STATUS register in bank 0. Stores the PCLATH register. Executes the interrupt service routine code (User-generated). Restores the STATUS register (and bank select bit). Restores the W and PCLATH registers.
An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 4.0) 9.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2)
EXAMPLE 9-1:
MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF BCF MOVF MOVWF : :(ISR) : MOVF MOVWF SWAPF MOVWF SWAPF SWAPF
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
;Copy W to TEMP register, could be bank one or zero ;Swap status to be saved into W ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 ;Save status to bank zero STATUS_TEMP register ;Only required if using pages 1, 2 and/or 3 ;Save PCLATH into W ;Page zero, regardless of current page ;Return to Bank 0 ;Copy FSR to W ;Copy FSR from W to FSR_TEMP
W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH STATUS, IRP FSR, W FSR_TEMP
PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
DS41106A-page 62
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
9.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running, on-chip, RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device have been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 9.1). WDT time-out period values may be found in the Electrical Specifications section under TWDT (parameter #31). Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.
. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 4-2) 0 WDT Timer 1 M U X Postscaler 8 8 - to - 1 MUX WDT Enable Bit PSA To TMR0 (Figure 4-2) 0 MUX 1 PSA PS2:PS0
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
WDT Time-out
FIGURE 9-16: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name 2007h 81h Config. bits
OPTION_REG
Bits 13:8 (1) N/A
Bit 7 -- RBPU
Bit 6 BODEN(1) INTEDG
Bit 5 CP1
Bit 4 CP0
Bit 3
Bit 2
Bit 1 FOSC1 PS1
Bit 0 FOSC0 PS0
PWRTE(1) WDTE PSA PS2
T0CS T0SE
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 9-1 for operation of these bits.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 63
PIC16C712/716
9.13 Power-down Mode (SLEEP)
Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 9.13.2 WAKE-UP USING INTERRUPTS Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and the disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 9.13.1 WAKE-UP FROM SLEEP
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some peripheral interrupts.
External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP capture mode interrupt. Special event trigger (Timer1 in asynchronous mode using an external clock).
DS41106A-page 64
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 9-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency (Note 2) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Note 1: 2: 3: 4:
XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
9.14
Program Verification/Code Protection
9.16
In-Circuit Serial ProgrammingTM
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices.
9.15
ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. For ROM devices, these values are submitted along with the ROM code.
PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details on serial programming, please refer to the In-Circuit Serial Programming (ICSPTM) Guide, (DS30277).
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 65
PIC16C712/716
NOTES:
DS41106A-page 66
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
10.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXXX instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 101 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 10-2 lists the instructions recognized by the MPASM assembler. Figure 10-1 shows the general formats that the instructions can have. Note: To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0 8 7 k (literal) 0 0
TABLE 10-1
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
0
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 Program Counter Time-out bit Power-down bit Zero bit Digit Carry bit Carry bit
d
PC TO PD Z DC C
k = 11-bit immediate value
The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction
A description of each instruction is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 67
PIC16C712/716
TABLE 10-2
Mnemonic, Operands
PIC16CXXX INSTRUCTION SET
Description Cycles MSb 14-Bit Opcode LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z TO,PD Z
TO,PD C,DC,Z Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
DS41106A-page 68
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
11.0
11.1
DEVELOPMENT SUPPORT
Development Tools
11.3
ICEPIC: Low-Cost PICmicro In-Circuit Emulator
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * MPLABTM -ICE Real-Time In-Circuit Emulator * ICEPICTM Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE(R) II Universal Programmer * PICSTART(R) Plus Entry-Level Prototype Programmer * SIMICE * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLABTM SIM Software Simulator * MPLAB-C17 (C Compiler) * Fuzzy Logic Development System (fuzzyTECH(R)-MP) * KEELOQ(R) Evaluation Kits and Programmer
ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through PentiumTM based machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation.
11.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode.
11.2
MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). MPLAB-ICE is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows(R) 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is available in two versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed range of the PICmicro MCU.
11.5
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 69
PIC16C712/716
11.6 SIMICE Entry-Level Hardware Simulator 11.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip's simulator MPLABTM-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology's MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchip's PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entrylevel system development.
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
11.7
PICDEM-1 Low-Cost PICmicro Demonstration Board
11.9
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
DS41106A-page 70
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
11.10 MPLAB Integrated Development Environment Software 11.12 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.
11.13
MPLAB-C17 Compiler
The MPLAB-C17 Code Development System is a complete ANSI `C' compiler and integrated development environment for Microchip's PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.
11.14
Fuzzy Logic Development System (fuzzyTECH-MP)
11.11
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from MPLABICE, Microchip's Universal Emulator System. MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip's fuzzyLABTM demonstration board for hands-on experience with fuzzy logic systems implementation.
11.15
SEEVAL(R) Evaluation and Programming System
The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart SerialsTM and secure serials. The Total EnduranceTM Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 71
PIC16C712/716
11.16 KEELOQ(R) Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS41106A-page 72
Preliminary
(c) 1999 Microchip Technology Inc.
TABLE 11-1
PIC12C5XX
PIC14000
PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X
PIC16C9XX PIC17C4X PIC17C7XX
24CXX 25CXX 93CXX
HCS200 HCS300 HCS301
MPLABTM-ICE
a
a
a
a
a
a
a
a
a
a
Emulator Products
Software Tools
Programmers
Demo Boards
(c) 1999 Microchip Technology Inc.
ICEPICTM Low-Cost In-Circuit Emulator
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
MPLABTM Integrated Development Environment
MPLABTM C17* Compiler
a
a
a
a
a
a
a
a
a
a
a
fuzzyTECH(R)-MP Explorer/Edition Fuzzy Logic Dev. Tool
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary
Total EnduranceTM Software Model
a
a a a a a a
a
a
a
a
a
a
a
a
a
PICSTART(R)Plus Low-Cost Universal Dev. Kit
a
a
a
a
a
a
a
PRO MATE(R) II Universal Programmer
KEELOQ(R) Programmer
a
SEEVAL(R) Designers Kit
a
SIMICE
a
a
PICDEM-14A
a
PICDEM-1
a
a
a
a
PICDEM-2
a
a
PICDEM-3
a
KEELOQ(R) Evaluation Kit
a
PIC16C712/716
DS41106A-page 73
KEELOQ Transponder Kit
a
PIC16C712/716
NOTES:
DS41106A-page 74
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
12.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings () Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1)(PDIP and SOIC) ....................................................................................................1.0W Total power dissipation (Note 1)(SSOP) .................................................................................................................0.65W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA and PORTB (combined) .................................................................................200 mA Maximum current sourced by PORTA and PORTB (combined)............................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 75
PIC16C712/716
FIGURE 12-1: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40C < TA < +125C
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20 25
FIGURE 12-2: PIC16LC712/716 VOLTAGE-FREQUENCY GRAPH, 0C < TA < +70C
6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20 25
DS41106A-page 76
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
12.1 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial +85C for industrial -40C TA +125C for extended -40C TA Characteristic Supply Voltage RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset voltage trip point Supply Current(2,5) Power-down Current(3,5) Min 4.0 VBOR* 0.05 TBD 3.65 0 0 0 0 Typ 1.5 VSS 0.8 4.0 10.5 1.5 1.5 2.5 6.0 TBD -- -- -- -- Max 5.5 5.5 4.35 2.5 8.0 42 16 19 19 20 200 200 4 4 20 Units V V V V V/ms See section on Power-on Reset for details PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details BODEN bit set FOSC = 4 MHz, VDD = 4.0V FOSC = 20 MHz, VDD = 4.0V VDD = 4.0V, WDT enabled,-40C to +85C VDD = 4.0V, WDT disabled, 0C to +70C VDD = 4.0V, WDT disabled,-40C to +85C VDD = 4.0V, WDT disabled,-40C to +125C WDTE bit set, VDD = 4.0V BODEN bit set, VDD = 5.0V All temperatures All temperatures All temperatures All temperatures Conditions
DC CHARACTERISTICS
Param No. D001 D001A D002* D003 D004* D004A* D005 D010 D013 D020 D021 D021B D022* D022A* 1A
Sym VDD VDR VPOR SVDD
BOR enabled (Note 7)
VBOR IDD IPD
V mA mA A A A A A A KHz MHz MHz MHz
IWDT IBOR FOSC
Module Differential Current(6) Watchdog Timer Brown-out Reset LP Oscillator Operating Frequency RC Oscillator Operating Frequency XT Oscillator Operating Frequency HS Oscillator Operating Frequency
* Note1: 2:
3: 4: 5: 6: 7:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to this trip point.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 77
PIC16C712/716
12.2 DC Characteristics: PIC16LC712/716-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial +85C for industrial -40C TA Characteristic Supply Voltage RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset voltage trip point Supply Current(2,5) Min 2.5 VBOR* 0.05 TBD 3.65 IPD Power-down Current(3,5) 0 0 0 0 Typ 1.5 VSS 2.0 22.5 7.5 0.9 0.9 6.0 TBD -- -- -- -- Max 5.5 5.5 4.35 3.8 48 30 5 5 20 200 200 4 4 20 Units V V V V V/ms See section on Power-on Reset for details PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details BODEN bit set XT, RC osc modes FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc mode FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C WDTE bit set, VDD = 4.0V BODEN bit set, VDD = 5.0V All temperatures All temperatures All temperatures All temperatures Conditions
DC CHARACTERISTICS Param No. D001 D002* D003 D004* D004A* D005 D010 D010A D020 D021 D021A D022* D022A* 1A Sym VDD VDR VPOR SVDD
BOR enabled (Note 7)
VBOR IDD
V mA A A A A A A KHz MHz MHz MHz
IWDT IBOR FOSC
Module Differential Current(6) Watchdog Timer Brown-out Reset LP Oscillator Operating Frequency RC Oscillator Operating Frequency XT Oscillator Operating Frequency HS Oscillator Operating Frequency
* Note1: 2:
3: 4: 5: 6: 7:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to this trip point.
DS41106A-page 78
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
12.3 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712716-20 (Commercial, Industrial, Extended) PIC16LC712/716-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) +70C for commercial Operating temperature 0C TA -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2 Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Sym
Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP modes) Input High Voltage I/O ports with TTL buffer
VIL D030 D030A D031 D032 D033
VSS VSS VSS Vss Vss
-
0.8V 0.15VDD 0.2VDD 0.2VDD 0.3VDD
V V V V V
4.5V VDD 5.5V otherwise
Note1
VIH D040 D040A
2.0 0.25VDD + 0.8V
-
VDD VDD
V V
4.5V VDD 5.5V otherwise
D041 D042 D042A D043
D060 D061 D063 D070 D080
IIL
with Schmitt Trigger buffer 0.8VDD MCLR 0.8VDD OSC1 (XT, HS and LP modes) 0.7VDD OSC1 (in RC mode) 0.9VDD Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 50 -
-
VDD VDD VDD VDD
V V V V
For entire VDD range Note1
250 -
1 5 5 400 0.6 0.6 0.6 0.6
A A A A V V V V
IPURB VOL
PORTB weak pull-up current Output Low Voltage I/O ports
Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc modes VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C
D083
OSC2/CLKOUT (RC osc mode)
-
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
*
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 79
PIC16C712/716
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial +85C for industrial -40C TA -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2 Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No. D090
Sym
Characteristic Output High Voltage I/O ports (Note 3)
VOH
VDD-0.7 VDD-0.7
-
8.5
V V V V V
D092
OSC2/CLKOUT (RC osc mode)
VDD-0.7 VDD-0.7
D150*
D100
Open-Drain High Voltage Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
VOD
-
IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin
-
-
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
All I/O pins and OSC2 (in RC 50 pF mode) * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
CIO
DS41106A-page 80
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
12.4
12.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid Hi-impedance
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 81
PIC16C712/716
12.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 12-1 apply to all timing specifications, unless otherwise noted. Figure 12-1 specifies the load conditions for the timing specifications.
TABLE 12-1
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature 0C TA +70C for commercial -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2. LC parts operate for commercial/industrial temp's only.
AC CHARACTERISTICS
FIGURE 12-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 VDD/2 CL VSS Pin VSS CL RL = 464 CL = 50 pF 15 pF for all pins except OSC2/CLKOUT for OSC2 output Load condition 2
RL
Pin
DS41106A-page 82
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
12.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 12-2: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 2 3 3 4 4
CLKOUT
TABLE 12-2
Param No. 1A Sym FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKIN Frequency (Note 1) Min DC DC DC DC Oscillator Frequency (Note 1) DC 0.1 4 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4 4 20 200 4 4 20 200 -- -- -- -- -- 10,000 250 250 -- DC -- -- -- 25 50 15 Units Conditions MHz MHz MHz kHz MHz MHz MHz kHz ns ns ns s ns ns ns ns s ns ns s ns ns ns ns RC and XT osc modes HS osc mode (-04) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode RC and XT osc modes HS osc mode (-04) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode (-04) HS osc mode (-20) LP osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
1
TOSC
External CLKIN Period (Note 1)
250 250 50 5
Oscillator Period (Note 1)
250 250 250 50 5
2 3*
TCY TosL, TosH TosR, TosF
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
200 100 2.5 15 -- -- --
4*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
*
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 83
PIC16C712/716
FIGURE 12-3: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 18 12 16 11 Q1 Q2 Q3
20, 21 Note: Refer to Figure 12-1 for load conditions.
TABLE 12-3
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 18A* 19* 20* 20A* 21* 21A* 22* 23* TINP TRBP TioF Sym
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Standard Extended (LC) Standard Extended (LC) Port output fall time INT pin high or low time RB7:RB4 change INT high or low time Standard Extended (LC) Min -- -- -- -- -- Tosc + 200 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 150 -- -- -- 40 80 40 80 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI TioV2osH TioR
TosH2ckH OSC1 to CLKOUT
Port input valid to OSC1 (I/O in setup time) Port output rise time
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edge. Note1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
*
DS41106A-page 84
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer RESET 34 I/O Pins Note: Refer to Figure 12-1 for load conditions. 32 30
31
34
FIGURE 12-5: BROWN-OUT RESET TIMING
BVDD VDD 35
TABLE 12-4
Parameter No. 30 31* 32 33* 34 35 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Sym TmcL TWDT TOST TPWRT TIOZ TBOR Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or WDT reset Brown-out Reset Pulse Width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units Conditions
s
ms -- ms
VDD = 5V, -40C to +125C VDD = 5V, -40C to +125C TOSC = OSC1 period VDD = 5V, -40C to +125C
s s
VDD BVDD (D005)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 85
PIC16C712/716
FIGURE 12-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 42 T1OSO/T1CKI
41
45 47 TMR0 or TMR1
Note: Refer to Figure 12-1 for load conditions.
46 48
TABLE 12-5
Param No. 40* 41* 42* Sym Tt0H
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Units Conditions ns ns ns ns ns ns Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4,..., 256) Must also meet parameter 47
45*
46*
47*
48
10 Tt0L T0CKI Low Pulse Width 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 15 Synchronous, Standard Prescaler = 25 Extended (LC) 2,4,8 30 Asynchronous Standard 50 Extended (LC) Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 15 Synchronous, Standard Prescaler = 25 Extended (LC) 2,4,8 30 Asynchronous Standard 50 Extended (LC) Greater of: Tt1P T1CKI input period Synchronous Standard 30 OR TCY + 40 N Extended (LC) Greater of: 50 OR TCY + 40 N 60 Asynchronous Standard 100 Extended (LC) Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
Must also meet parameter 47
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
-- -- -- --
-- -- 200 7Tosc
ns ns kHz --
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41106A-page 86
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 12-7: CAPTURE/COMPARE/PWM TIMINGS
CCP1 (Capture Mode)
50 52
51
CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 12-1 for load conditions. 54
TABLE 12-6
Param No. 50*
CAPTURE/COMPARE/PWM REQUIREMENTS
Min No Prescaler With Prescaler Standard Extended (LC) 0.5TCY + 20 10 20 0.5TCY + 20 Standard Extended (LC) 10 20 3TCY + 40 N Standard Extended (LC) -- -- -- -- Typ Max Units Conditions -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 45 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4, or 16)
Sym Characteristic TccL CCP1 input low time
51*
TccH CCP1 input high time
No Prescaler With Prescaler
52* 53*
TccP CCP1 input period TccR CCP1 output rise time
54*
TccF CCP1 output fall time
Standard Extended (LC)
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 87
PIC16C712/716
TABLE 12-7 A/D CONVERTER CHARACTERISTICS: PIC16C712/716-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C712/716-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC712/716-04 (COMMERCIAL, INDUSTRIAL)
Min -- -- -- -- -- -- -- 2.5V VSS - 0.3 -- -- -- 10 Typ -- -- -- -- -- -- guaranteed (Note 3) -- -- -- 180 90 -- Max 8-bits <1 <1 <1 <1 <1 -- VDD + 0.3 VREF + 0.3 10.0 -- -- 1000 Units bit LSb LSb LSb LSb LSb -- V V k A A A Average current consumption when A/D is on. (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 9.1. During A/D Conversion cycle Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VSS VAIN VREF
Param Sym Characteristic No. A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 NR Resolution
EABS Total Absolute error EIL Integral linearity error
EDL Differential linearity error EFS Full scale error EOFF Offset error -- Monotonicity
VREF Reference voltage VAIN Analog input voltage ZAIN Recommended impedance of analog voltage source IAD A/D conversion current (VDD) Standard Extended (LC)
A50
IREF VREF input current (Note 2)
-- 2: 3:
--
10
A
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
DS41106A-page 88
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 12-8: A/D CONVERSION TIMING
BSF ADCON0, GO 134 Q4 130 A/D CLK 132 (TOSC/2) (1) 131
1 Tcy
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO SAMPLING STOPPED DONE
SAMPLE
Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-8
Param No. 130
A/D CONVERSION REQUIREMENTS
Min Standard Extended (LC) Standard Extended (LC) 1.6 2.0 2.0 3.0 11 Note 2 5* Typ -- -- 4.0 6.0 -- 20 -- Max -- -- 6.0 9.0 11 -- -- Units s s s s TAD s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC Mode A/D RC Mode
Sym Characteristic TAD A/D clock period
131 132
TCNV Conversion time (not including S/H time) (Note 1) TACQ Acquisition time
134
TGO
Q4 to A/D clock start
--
TOSC/2
--
--
135 : :
TSWC Switching from convert sample time
1.5
--
--
TAD
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. : This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 9.1 for min conditions.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 89
PIC16C712/716
NOTES:
DS41106A-page 90
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'min' represents (mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
Graphs and Tables not available at this time.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 91
PIC16C712/716
NOTES:
DS41106A-page 92
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
14.0
14.1
PACKAGING INFORMATION
Package Marking Information 18-Lead PDIP Example PIC16C716-04/P 9917HAT
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX AABBCDE
18-Lead CERDIP Windowed XXXXXXXX XXXXXXXX AABBCDE 18-Lead SOIC Example
16C716 /JW 9917CAT
Example PIC16C712 -20/SO 9910/SAA Example PIC16C712 -20I/SS025 9917SBP
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE
20-Lead SSOP
XXXXXXXXXX XXXXXXXXXX
AABBCDE
Legend: MM...M XX...X AA BB C
D E Note:
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5" Line S = 6" Line H = 8" Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 93
PIC16C712/716
Package Type: K04-007 18-Lead Plastic Dual In-line (P) - 300 mil
E
D
2 n E1 A1 A R c A2 B1 eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter.
1
L
B
p
MIN n p B B1 R c A A1 A2 L D E E1 eB
INCHES* NOM 0.300 18 0.100 0.013 0.018 0.055 0.060 0.000 0.005 0.005 0.010 0.110 0.155 0.075 0.095 0.000 0.020 0.125 0.130 0.890 0.895 0.245 0.255 0.230 0.250 0.310 0.349 5 10 5 10
MAX
MIN
0.023 0.065 0.010 0.015 0.155 0.115 0.020 0.135 0.900 0.265 0.270 0.387 15 15
MILLIMETERS NOM MAX 7.62 18 2.54 0.33 0.46 0.58 1.40 1.52 1.65 0.00 0.13 0.25 0.13 0.25 0.38 2.79 3.94 3.94 1.91 2.41 2.92 0.00 0.51 0.51 3.18 3.30 3.43 22.61 22.73 22.86 6.22 6.48 6.73 5.84 6.35 6.86 7.87 8.85 9.83 5 10 15 5 10 15
Dimension "B1" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B1."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E." JEDEC equivalent: MS-001 AC
DS41106A-page 94
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
Package Type: K04-010 18-Lead Ceramic Dual In-line with Window (JW) - 300 mil
E
W2
D
2 n W1 E1 1
A R
A1 L
c eB A2 B1 B p
Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Width Window Length
MIN n p B B1 R c A A1 A2 L D E E1 eB W1 W2
0.098 0.016 0.050 0.010 0.008 0.175 0.091 0.015 0.125 0.880 0.285 0.255 0.345 0.130 0.190
INCHES* NOM 0.300 18 0.100 0.019 0.055 0.013 0.010 0.183 0.111 0.023 0.138 0.900 0.298 0.270 0.385 0.140 0.200
MAX
MIN
0.102 0.021 0.060 0.015 0.012 0.190 0.131 0.030 0.150 0.920 0.310 0.285 0.425 0.150 0.210
MILLIMETERS NOM MAX 7.62 18 2.59 2.49 2.54 0.53 0.41 0.47 1.52 1.27 1.40 0.38 0.25 0.32 0.30 0.20 0.25 4.83 4.64 4.45 3.33 2.82 2.31 0.76 0.57 0.00 3.81 3.49 3.18 23.37 22.35 22.86 7.87 7.56 7.24 7.24 6.86 6.48 9.78 10.80 8.76 0.15 0.14 0.13 0.2 0.21 0.19
* Controlling Parameter. JEDEC equivalent: MO-036 AE
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 95
PIC16C712/716
Package Type: K04-051 18-Lead Plastic Small Outline (SO) - Wide, 300 mil
E1 p E
D
2 B n X 45 1
L R2
c A R1 Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
A1
L1
A2 MILLIMETERS NOM MAX 1.27 18 2.36 2.64 2.50 1.22 1.73 1.47 0.10 0.28 0.19 11.43 11.73 11.58 7.42 7.59 7.51 10.01 10.64 10.33 0.74 0.25 0.50 0.13 0.13 0.25 0.13 0.25 0.13 0.28 0.41 0.53 0 4 8 0.25 0.38 0.51 0.23 0.30 0.27 0.36 0.48 0.42 0 12 15 0 12 15
MIN p n A A1 A2 D E E1 X R1 R2 L L1 c B
INCHES* NOM 0.050 18 0.093 0.099 0.048 0.058 0.004 0.008 0.450 0.456 0.292 0.296 0.394 0.407 0.010 0.020 0.005 0.005 0.005 0.005 0.011 0.016 0 4 0.010 0.015 0.009 0.011 0.014 0.017 0 12 0 12
MAX
MIN
0.104 0.068 0.011 0.462 0.299 0.419 0.029 0.010 0.010 0.021 8 0.020 0.012 0.019 15 15
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E." JEDEC equivalent: MS-013 AB
DS41106A-page 96
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) - 5.30 mm
E1 E p
D
B n
2 1 L R2
c
A A1 R1 L1 A2
Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
*
MIN p n A A1 A2 D E E1 R1 R2 L L1 c B
INCHES NOM 0.026 20 0.068 0.073 0.026 0.036 0.002 0.005 0.278 0.283 0.205 0.208 0.301 0.306 0.005 0.005 0.005 0.005 0.015 0.020 4 0 0.000 0.005 0.005 0.007 0.010 0.012 0 5 0 5
MAX
MIN
0.078 0.046 0.008 0.289 0.212 0.311 0.010 0.010 0.025 8 0.010 0.009 0.015 10 10
MILLIMETERS* NOM MAX 0.65 20 1.86 1.99 1.73 0.91 1.17 0.66 0.13 0.21 0.05 7.20 7.33 7.07 5.29 5.38 5.20 7.78 7.90 7.65 0.13 0.25 0.13 0.13 0.25 0.13 0.51 0.64 0.38 4 0 8 0.13 0.25 0.00 0.18 0.22 0.13 0.32 0.38 0.25 0 5 10 0 5 10
Controlling Parameter. Dimension "B" does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003" (0.076 mm) per side or 0.006" (0.152 mm) more than dimension "B."
Dimensions "D" and "E" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions "D" or "E." JEDEC equivalent: MO-150 AE
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 97
PIC16C712/716
NOTES:
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 98
PIC16C712/716
APPENDIX A: REVISION HISTORY
Version A Date 2/99 Revision Description This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234, and the PIC16C7X Data Sheet, DS30390. 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. PORTB has weak pull-ups and interrupt on change feature. 13. T0CKI pin is also a port pin (RA4) now. 14. FSR is made a full eight bit register. 15. "In-circuit serial programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). 16. PCON status register is added with a Power-on Reset status bit (POR). 17. Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. 18. Brown-out protection circuitry has been added. Controlled by configuration word bit BODEN. Brown-out reset ensures the device is placed in a reset condition if VDD dips below a fixed setpoint. To convert code written for PIC16C5X to PIC16CXXX, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h.
APPENDIX B: CONVERSION CONSIDERATIONS
There are no previous versions of this device.
APPENDIX C: MIGRATION FROM BASE-LINE TO MID-RANGE DEVICES
This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a mid-range device (i.e., PIC16CXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). 2. A PC high latch register (PCLATH) is added to handle program memory paging. Bits PA2, PA1, PA0 are removed from STATUS register. 3. Data memory paging is redefined slightly. STATUS register is modified. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. 5. OPTION_REG and TRIS registers are made addressable. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. Reset vector is changed to 0000h. 9. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. 10. Wake up from SLEEP through interrupt is added. 1.
3. 4. 5.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 99
PIC16C712/716
NOTES:
DS41106A-page 100
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
INDEX A
A/D ..................................................................................... 45 A/D Converter Enable (ADIE Bit) ............................... 16 A/D Converter Flag (ADIF Bit) ............................. 17, 47 A/D Converter Interrupt, Configuring ......................... 47 ADCON0 Register ................................................ 11, 45 ADCON1 Register .......................................... 12, 45, 46 ADRES Register ............................................ 11, 45, 47 Analog Port Pins, Configuring .................................... 49 Block Diagram ............................................................ 47 Block Diagram, Analog Input Model ........................... 48 Channel Select (CHS2:CHS0 Bits) ............................ 45 Clock Select (ADCS1:ADCS0 Bits) ............................ 45 Configuring the Module .............................................. 47 Conversion Clock (TAD) ............................................. 49 Conversion Status (GO/DONE Bit) ...................... 45, 47 Conversions ............................................................... 50 Converter Characteristics .......................................... 88 Module On/Off (ADON Bit) ......................................... 45 Port Configuration Control (PCFG2:PCFG0 Bits) ...... 46 Sampling Requirements ............................................. 48 Special Event Trigger (CCP) ................................ 41, 50 Timing Diagram .......................................................... 89 Absolute Maximum Ratings ............................................... 75 ADCON0 Register ........................................................ 11, 45 ADCS1:ADCS0 Bits ................................................... 45 ADON Bit ................................................................... 45 CHS2:CHS0 Bits ........................................................ 45 GO/DONE Bit ....................................................... 45, 47 ADCON1 Register .................................................. 12, 45, 46 PCFG2:PCFG0 Bits ................................................... 46 ADRES Register .................................................... 11, 45, 47 Architecture PIC16C62B/PIC16C72A Block Diagram ...................... 5 Assembler MPASM Assembler .................................................... 71 Code Protection ........................................................... 51, 65 CP1:CP0 Bits ............................................................. 52 Compare (CCP Module) .................................................... 41 Block Diagram ........................................................... 41 CCP Pin Configuration .............................................. 41 CCPR1H:CCPR1L Registers .................................... 41 Software Interrupt ...................................................... 41 Special Event Trigger .................................... 34, 41, 50 Timer1 Mode Selection .............................................. 41 Configuration Bits .............................................................. 51 Conversion Considerations ................................................ 99
D
Data Memory ..................................................................... 10 Bank Select (RP1:RP0 Bits) ................................ 10, 13 General Purpose Registers ....................................... 10 Register File Map ...................................................... 10 Special Function Registers ........................................ 11 DC Characteristics ....................................................... 77, 79 Development Support ........................................................ 69 Development Tools ............................................................ 69 Direct Addressing .............................................................. 20
E
Electrical Characteristics ................................................... 75 Errata ................................................................................... 3 External Power-on Reset Circuit ........................................ 55
F
Family of Devices PIC16C7XX ................................................................. 2 Firmware Instructions ........................................................ 67 Fuzzy Logic Dev. System (fuzzyTECH(R)-MP) ................... 71
I
I/O Ports ............................................................................ 21 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 69 ID Locations ................................................................. 51, 65 In-Circuit Serial Programming (ICSP) .......................... 51, 65 Indirect Addressing ............................................................ 20 FSR Register ................................................. 10, 11, 20 INDF Register ............................................................ 11 Instruction Format .............................................................. 67 Instruction Set .................................................................... 67 Summary Table ......................................................... 68 INTCON Register ......................................................... 11, 15 GIE Bit ....................................................................... 15 INTE Bit ..................................................................... 15 INTF Bit ..................................................................... 15 PEIE Bit ..................................................................... 15 RBIE Bit ..................................................................... 15 RBIF Bit ............................................................... 15, 24 T0IE Bit ...................................................................... 15 T0IF Bit ...................................................................... 15 Interrupt Sources ......................................................... 51, 61 A/D Conversion Complete ......................................... 47 Block Diagram ........................................................... 61 Capture Complete (CCP) .......................................... 40 Compare Complete (CCP) ........................................ 41 Interrupt on Change (RB7:RB4 ) ............................... 24 RB0/INT Pin, External ............................................... 62 TMR0 Overflow .................................................... 30, 62 TMR1 Overflow .................................................... 31, 34 TMR2 to PR2 Match .................................................. 37 TMR2 to PR2 Match (PWM) ................................ 36, 42 Interrupts, Context Saving During ...................................... 62 Interrupts, Enable Bits
B
Banking, Data Memory ................................................ 10, 13 Brown-Out Detect (BOD) ................................................... 55 Brown-out Reset (BOR) ................................... 51, 54, 58, 59 BOR Enable (BODEN Bit) .......................................... 52 BOR Status (BOR Bit) ................................................ 18 Timing Diagram .......................................................... 85
C
Capture (CCP Module) ...................................................... 40 Block Diagram ............................................................ 40 CCP Pin Configuration ............................................... 40 CCPR1H:CCPR1L Registers ..................................... 40 Changing Between Capture Prescalers ..................... 40 Software Interrupt ...................................................... 40 Timer1 Mode Selection .............................................. 40 Capture/Compare/PWM (CCP) .......................................... 39 CCP1CON Register ............................................. 11, 39 CCPR1H Register ................................................ 11, 39 CCPR1L Register ................................................ 11, 39 Enable (CCP1IE Bit) .................................................. 16 Flag (CCP1IF Bit) ....................................................... 17 Timer Resources ........................................................ 39 Timing Diagram .......................................................... 87 CCP1CON Register ........................................................... 39 CCP1M3:CCP1M0 Bits .............................................. 39 CCP1X:CCP1Y Bits ................................................... 39
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 101
PIC16C712/716
A/D Converter Enable (ADIE Bit) ............................... 16 CCP1 Enable (CCP1IE Bit) .................................. 16, 40 Global Interrupt Enable (GIE Bit) ......................... 15, 61 Interrupt on Change (RB7:RB4) Enable (RBIE Bit) ................................................. 15, 62 Peripheral Interrupt Enable (PEIE Bit) ....................... 15 RB0/INT Enable (INTE Bit) ........................................ 15 TMR0 Overflow Enable (T0IE Bit) .............................. 15 TMR1 Overflow Enable (TMR1IE Bit) ........................ 16 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16 Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) ............................. 17, 47 CCP1 Flag (CCP1IF Bit) ................................ 17, 40, 41 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ............................................... 15, 24, 62 RB0/INT Flag (INTF Bit) ............................................. 15 TMR0 Overflow Flag (T0IF Bit) ............................ 15, 62 TMR1 Overflow Flag (TMR1IF Bit) ............................ 17 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 17 Pin Functions MCLR/Vpp ................................................................... 6 RA0/AN0 ...................................................................... 6 RA1/AN1 ...................................................................... 6 RA2/AN2 ...................................................................... 6 RA3/AN3/Vref .............................................................. 6 RA4/T0CKI .................................................................. 6 RB0/INT ....................................................................... 7 RB1 .............................................................................. 7 RB2 .............................................................................. 7 RB3 .............................................................................. 7 RB4 .............................................................................. 7 RB5 .............................................................................. 7 RB6 .............................................................................. 7 RB7 .............................................................................. 7 Vdd .............................................................................. 7 Vss ............................................................................... 7 Pinout Descriptions PIC16C62B/PIC16C72A .............................................. 6 PIR1 Register .............................................................. 11, 17 ADIF Bit ..................................................................... 17 CCP1IF Bit ................................................................. 17 TMR1IF Bit ................................................................. 17 TMR2IF Bit ................................................................. 17 Pointer, FSR ...................................................................... 20 PORTA Initialization ................................................................ 21 PORTA Register .................................................. 11, 21 RA3:RA0 and RA5 Port Pins ..................................... 21 RA4/T0CKI Pin .......................................................... 22 TRISA Register .................................................... 12, 21 PORTB Initialization ................................................................ 23 PORTB Register .................................................. 11, 23 Pull-up Enable (RBPU Bit) ......................................... 14 RB0/INT Edge Select (INTEDG Bit) .......................... 14 RB0/INT Pin, External ................................................ 62 RB3:RB0 Port Pins .................................................... 23 RB7:RB4 Interrupt on Change ................................... 62 RB7:RB4 Interrupt on Change Enable (RBIE Bit) 15, 62 RB7:RB4 Interrupt on Change Flag (RBIF Bit) ............................................... 15, 24, 62 RB7:RB4 Port Pins .................................................... 26 TRISB Register .................................................... 12, 23 PORTC Block Diagram ..................................................... 24, 25 TRISC Register .......................................................... 12 Postscaler, Timer2 Select (TOUTPS3:TOUTPS0 Bits) ............................ 36 Postscaler, WDT ................................................................ 29 Assignment (PSA Bit) .......................................... 14, 29 Block Diagram ........................................................... 30 Rate Select (PS2:PS0 Bits) ................................. 14, 29 Switching Between Timer0 and WDT ........................ 30 Power-on Reset (POR) .............................. 51, 54, 55, 58, 59 Oscillator Start-up Timer (OST) ........................... 51, 55 POR Status (POR Bit) ............................................... 18 Power Control (PCON) Register ................................ 57 Power-down (PD Bit) ........................................... 13, 54 Power-on Reset Circuit, External ............................... 55 Power-up Timer (PWRT) ..................................... 51, 55 PWRT Enable (PWRTE Bit) ...................................... 52 Time-out (TO Bit) ................................................. 13, 54 Time-out Sequence ................................................... 57 Time-out Sequence on Power-up .............................. 60 Timing Diagram ......................................................... 85
K
KeeLoq(R) Evaluation and Programming Tools ................... 72
M
Master Clear (MCLR) MCLR Reset, Normal Operation .................... 54, 58, 59 MCLR Reset, SLEEP ..................................... 54, 58, 59 Memory Organization Data Memory ............................................................. 10 Program Memory ......................................................... 9 MPLAB Integrated Development Environment Software ... 71
O
OPCODE Field Descriptions .............................................. 67 OPTION_REG Register ............................................... 12, 14 INTEDG Bit ................................................................ 14 PS2:PS0 Bits ....................................................... 14, 29 PSA Bit ................................................................. 14, 29 RBPU Bit .................................................................... 14 T0CS Bit ............................................................... 14, 29 T0SE Bit ............................................................... 14, 29 Oscillator Configuration ................................................ 51, 53 HS ........................................................................ 53, 58 LP ......................................................................... 53, 58 RC .................................................................. 53, 54, 58 Selection (FOSC1:FOSC0 Bits) ................................. 52 XT ........................................................................ 53, 58 Oscillator, Timer1 ......................................................... 31, 34 Oscillator, WDT .................................................................. 63
P
Packaging .......................................................................... 93 Paging, Program Memory .............................................. 9, 19 PCON Register ............................................................ 18, 57 BOR Bit ...................................................................... 18 POR Bit ...................................................................... 18 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 70 PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 70 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 70 PICSTART(R) Plus Entry Level Development System ........ 69 PIE1 Register ............................................................... 12, 16 ADIE Bit ..................................................................... 16 CCP1IE Bit ................................................................. 16 TMR1IE Bit ................................................................. 16 TMR2IE Bit ................................................................. 16
DS41106A-page 102
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
Prescaler, Capture ............................................................. 40 Prescaler, Timer0 ............................................................... 29 Assignment (PSA Bit) .......................................... 14, 29 Block Diagram ............................................................ 30 Rate Select (PS2:PS0 Bits) ................................. 14, 29 Switching Between Timer0 and WDT ........................ 30 Prescaler, Timer1 ............................................................... 32 Select (T1CKPS1:T1CKPS0 Bits) .............................. 31 Prescaler, Timer2 ............................................................... 42 Select (T2CKPS1:T2CKPS0 Bits) .............................. 36 PRO MATE(R) II Universal Programmer ............................. 69 Product Identification System .......................................... 107 Program Counter PCL Register ........................................................ 11, 19 PCLATH Register .......................................... 11, 19, 62 Reset Conditions ........................................................ 58 Program Memory ................................................................. 9 Interrupt Vector ............................................................ 9 Paging .................................................................... 9, 19 Program Memory Map ................................................. 9 Reset Vector ................................................................ 9 Program Verification .......................................................... 65 Programming, Device Instructions ..................................... 67 PWM (CCP Module) .......................................................... 42 Block Diagram ............................................................ 42 CCPR1H:CCPR1L Registers ..................................... 42 Duty Cycle .................................................................. 42 Example Frequencies/Resolutions ............................ 43 Output Diagram .......................................................... 42 Period ......................................................................... 42 Set-Up for PWM Operation ........................................ 43 TMR2 to PR2 Match ............................................ 36, 42 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 17
T
T1CON Register .......................................................... 11, 31 T1CKPS1:T1CKPS0 Bits ........................................... 31 T1OSCEN Bit ............................................................ 31 T1SYNC Bit ............................................................... 31 TMR1CS Bit ............................................................... 31 TMR1ON Bit .............................................................. 31 T2CON Register .......................................................... 11, 36 T2CKPS1:T2CKPS0 Bits ........................................... 36 TMR2ON Bit .............................................................. 36 TOUTPS3:TOUTPS0 Bits ......................................... 36 Timer0 ............................................................................... 29 Block Diagram ........................................................... 29 Clock Source Edge Select (T0SE Bit) ................. 14, 29 Clock Source Select (T0CS Bit) .......................... 14, 29 Overflow Enable (T0IE Bit) ........................................ 15 Overflow Flag (T0IF Bit) ...................................... 15, 62 Overflow Interrupt ................................................ 30, 62 Timing Diagram ......................................................... 86 TMR0 Register .......................................................... 11 Timer1 ............................................................................... 31 Block Diagram ........................................................... 32 Capacitor Selection ................................................... 34 Clock Source Select (TMR1CS Bit) ........................... 31 External Clock Input Sync (T1SYNC Bit) ................... 31 Module On/Off (TMR1ON Bit) ................................... 31 Oscillator .............................................................. 31, 34 Oscillator Enable (T1OSCEN Bit) .............................. 31 Overflow Enable (TMR1IE Bit) .................................. 16 Overflow Flag (TMR1IF Bit) ....................................... 17 Overflow Interrupt ................................................ 31, 34 Special Event Trigger (CCP) ............................... 34, 41 T1CON Register .................................................. 11, 31 Timing Diagram ......................................................... 86 TMR1H Register .................................................. 11, 31 TMR1L Register .................................................. 11, 31 Timer2 Block Diagram ........................................................... 36 PR2 Register ................................................. 12, 36, 42 T2CON Register .................................................. 11, 36 TMR2 Register .................................................... 11, 36 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16 TMR2 to PR2 Match Flag (TMR2IF Bit) .................... 17 TMR2 to PR2 Match Interrupt ........................ 36, 37, 42 Timing Diagrams Time-out Sequence on Power-up .............................. 60 Wake-up from SLEEP via Interrupt ........................... 65 Timing Diagrams and Specifications ................................. 83 A/D Conversion ......................................................... 89 Brown-out Reset (BOR) ............................................. 85 Capture/Compare/PWM (CCP) ................................. 87 CLKOUT and I/O ....................................................... 84 External Clock ........................................................... 83 Oscillator Start-up Timer (OST) ................................. 85 Power-up Timer (PWRT) ........................................... 85 Reset ......................................................................... 85 Timer0 and Timer1 .................................................... 86 Watchdog Timer (WDT) ............................................. 85
Q
Q-Clock .............................................................................. 42
R
RAM. See Data Memory Register File ....................................................................... 10 Register File Map ............................................................... 10 Reset ............................................................................ 51, 54 Block Diagram ............................................................ 56 Reset Conditions for All Registers ............................. 59 Reset Conditions for PCON Register ......................... 58 Reset Conditions for Program Counter ...................... 58 Reset Conditions for STATUS Register ..................... 58 Timing Diagram .......................................................... 85 Revision History ................................................................. 99
S
SEEVAL(R) Evaluation and Programming System .............. 71 SLEEP ................................................................... 51, 54, 64 Software Simulator (MPLAB-SIM) ..................................... 71 Special Features of the CPU ............................................. 51 Special Function Registers ................................................ 11 Speed, Operating ................................................................. 1 Stack .................................................................................. 19 STATUS Register .................................................. 11, 13, 62 C Bit ........................................................................... 13 DC Bit ......................................................................... 13 IRP Bit ........................................................................ 13 PD Bit ................................................................... 13, 54 RP1:RP0 Bits ............................................................. 13 TO Bit ................................................................... 13, 54 Z Bit ............................................................................ 13
W
W Register ......................................................................... 62 Wake-up from SLEEP .................................................. 51, 64 Interrupts ............................................................. 58, 59 MCLR Reset .............................................................. 59 Timing Diagram ......................................................... 65 WDT Reset ................................................................ 59
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 103
PIC16C712/716
Watchdog Timer (WDT) ............................................... 51, 63 Block Diagram ............................................................ 63 Enable (WDTE Bit) ............................................... 52, 63 Programming Considerations .................................... 63 RC Oscillator .............................................................. 63 Time-out Period ......................................................... 63 Timing Diagram .......................................................... 85 WDT Reset, Normal Operation ...................... 54, 58, 59 WDT Reset, SLEEP ....................................... 54, 58, 59 WWW, On-Line Support ....................................................... 3
DS41106A-page 104
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-786-7302 for the rest of the world.
981103
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 105
PIC16C712/716
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C712/716 Questions: 1. What are the best features of this document? Y N Literature Number: DS41106A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS41106A-page 106
Preliminary
(c) 1999 Microchip Technology Inc.
PIC16C712/716
PIC16C712/716 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -XX X /XX Package XXX Pattern Examples: a)
b) Device PIC16C712(1), PIC16C712T(2);VDD range 4.0V to PIC16LC712(1), PIC16LC712T(2);VDD range 2.5V PIC16C716(1), PIC16C716T(2);VDD range 4.0V to (1) (2) 5.5V to 5.5V 5.5V PIC16LC716 , PIC16LC716T ;VDD range 2.5V to 5.5V c) PIC16C716 - 04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. PIC16LC712 - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. PIC16C712 - 20I/P = Industrial temp., PDIP package, 20MHz, normal VDD limits.
Frequency Temperature Range Range
Frequency Range
04 20
= 4 MHz = 20 MHz
Note 1: 2:
Temperature Range
blank I E
= 0C to 70C = -40C to +85C = -40C to +125C
(Commercial) (Industrial) (Extended)
3: 4:
= CMOS = Low Power CMOS = in tape and reel - SOIC, SSOP packages only. LC extended temperature device is not offered. LC is not offered at 20 MHz
C LC T
Package
JW SO P SS
= = = =
Windowed CERDIP SOIC PDIP SSOP
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices).
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
(c) 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 107
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com
AMERICAS (continued)
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835
Beijing
Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104
Chicago
Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
India
Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Denmark
Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Dallas
Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924
Japan
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
France
Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934
Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
Italy
Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
11/15/99
Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.

▲Up To Search▲

Price & Availability of PIC16C712

	To Download PIC16C712 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .